1. Technical Field
The present disclosure relates, in general, to an interposer substrate for semiconductor device packages and a method for making the same. More specifically, the present disclosure relates to a double embedded patterned interposer substrate and a double side via last manufacturing method for making the double embedded patterned substrate.
2. Description of the Related Art
There is continued demand for miniaturization, weight reduction, improved performance, improved reliability and lower costs in electronic products, such as for mobile phones and wearable electronics. Accordingly, improvements such as system-on-chip (SoC) packages have been developed. SoC packages integrate multiple functionalities at the chip level; however, designing and testing SoC packages can be difficult, and SoC manufacturing can be relatively high cost and low yield.
In addition to the demands on electronic products described above, demands on semiconductor devices in the electronic products include a demand for increased numbers of input/output signals. To accommodate large numbers of input/output signals, high density interconnect pitch can be implemented for adjoining semiconductor devices or substrates. However, the base substrate may also include a lower density interconnect pitch for connecting the input/output signals of a semiconductor device package to a system substrate (e.g. a printed circuit board (PCB) onto which the semiconductor device package substrate is mounted). It can be difficult to meet the requirements of both higher and lower density interconnect pitches in a base substrate.